Dmitry Ryabikov (RDSik)

RDSik

User data from Github https://github.com/RDSik

Company:Saint Petersburg State University of Telecommunications

Location:Saint Petersburg, Russia

GitHub:@RDSik

Dmitry Ryabikov's repositories

FPGA-Awesome-list

List of useful materials on FPGA topic

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verilog-transceiver

Educational project for the Xilinx ZedBoard Zynq-7000 Development Kit

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FPGA-Tools-Docker

Docker Container with Iverilog, Yosys, Verilator, Verible, Gowin Education and more.

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digital-design-lab-manual

Мое решение задач из книги Цифровой синтез: практический курс

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schoolRISCV

CPU microarchitecture, step by step

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si5340-config-loader

Module for load configuration from ClockBuilderPro to Si5340 PLL via i2c interface

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sv-modules

Some SV modules

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tm1638-verilog

A basic verilog driver for the TM1638 LED and key matrix chip

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FPGA_labs

Исходные коды к лаборатрному практикуму "Основы проектирования электронных средств на ПЛИС"

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