fsiddiqui85

Siddiqui's repositories

Security-Patterns

This repository is part of EU-funded Research Project (XANDAR)

Language:ShellGPL-3.02 20

The IPPro is a 16-bit signed fixed-point, five-stage balanced pipelined RISC architecture that exploits the DSP48E1 features and provides balance among performance, latency and efficient resource utilization.

Language:VerilogBSD-3-Clause1 10

XilinxZynq-ImageProcessing-Benchmarks

This repository contains the implementation of Image Processing Benchmarks running on Arm Cortex-A9 processor available in Xilinx Zynq 7000 SoC on Avent Zedboard.

Language:CBSD-3-Clause000