synopsys-vcs

There are 0 repository under synopsys-vcs topic.

OpenEDF / verilog-basic
learn the combinational and sequential logic circuit.
fpga fpga-programming ice40up5k iverilog simulation simulator synopsys-dc synopsys-vcs verilog vhdl
Language:SystemVerilog 17
tatan432 / AES_ENCODER
RTL implementation for Advanced Encryption Standard (AES) in Verilog. Synthesis Done in Synopsys DC.
aes-encryption aes-128 encription rtl verilog-project digital digital-design ee4415 synthesis synopsys-dc synopsys-vcs
Language:Verilog 9
vb000 / vcs-slave-mode
Example to control VCS simulation with a C/C++ program. This involves VCS output a shared object instead of an executable (simv).
synopsys-vcs verilog-simulator shared-object
Language:Makefile 5
cong2738 / May_team_project_I2C_SPI
UVM based Verification of SPI_Protocol and I2C_Protoccol. A Serial intra System Communication Peripheral Protocol
axi basys3-fpga c i2c microblaze spi synopsys-vcs systemverilog verdi verilog vivado hardware-description-language fpga uvm
Language:VHDL

OpenEDF / verilog-basic