synopsys-vcs

There are 0 repository under synopsys-vcs topic.

abdelazeem201 / ORCA
Multi-Voltage and Multi-Threshold Low Power Design Techniques for ORCA Processor Based on 32 nm Technology
asic pnr rtl synopsys synopsys-dc synopsys-vcs synthesis upf verilog vhdl synopsys-iccii saed32nm asic-design fpga-soc hdl systemonchip
Language:Verilog 12
OpenEDF / verilog-basic
learn the combinational and sequential logic circuit.
verilog fpga-programming fpga simulation simulator vhdl ice40up5k iverilog synopsys-dc synopsys-vcs
Language:SystemVerilog 10
tatan432 / AES_ENCODER
RTL implementation for Advanced Encryption Standard (AES) in Verilog. Synthesis Done in Synopsys DC.
aes-encryption aes-128 encription rtl verilog-project digital digital-design ee4415 synthesis synopsys-dc synopsys-vcs
Language:Verilog 8
vb000 / vcs-slave-mode
Example to control VCS simulation with a C/C++ program. This involves VCS output a shared object instead of an executable (simv).
synopsys-vcs verilog-simulator shared-object
Language:Makefile 4

abdelazeem201 / ORCA