stineje

James E. Stine's repositories

sky130RHBDlib

Open-source RHBD (Radiation Hardened by Design) Standard-Cell Library for SKY130

Language:TclApache-2.027 30

CharLib

Open-source repository for a standard-cell library characterizer using complete open-source tools

Language:PythonGPL-2.014 6 26

sky130_cds

This repository is an open-source version of SKY130 to help facilitate use of Cadence Design System tools for use with Skywater 130 Process Design Kit

Language:TclApache-2.011 2 1

ecen4303F23

Files associated with Digital Integrated Circuits (ecen4303) at Oklahoma State University

Language:TclMIT9 10

ecen4243S24

Spring 2023 ecen4243 Computer Architecture Lab Material

Language:HTMLMIT600

dldfall2023

This repository contains information about Digital Logic Design (ecen 3233) laboratory elements for Fall 2023.

Language:TeXMIT3 10

globalfoundries-pdk-libs-gf180mcu_osu_sc

Digital standard cells for GF180MCU provided by Oklahoma State University.

Language:TclApache-2.0300

HSCA_S24

High-Speed Computer Arithmetic Spring 2024 at Oklahoma State University

Language:CMIT300

prefix_adders

Prefix adder generators for Verilog

Language:PerlApache-2.03 1 1

osu-riscv

OSU Datapath/Control RV32 Single-Cycle and Pipelined Architecture in SV

Language:AssemblyMIT2 10

SpringerBookArith04

These are files from my 2004 book, "Digital Computer Arithmetic Datapath Design Using Verilog HDL"

Language:VerilogApache-2.02 10

xchiplogo

This is chiplogo a logo generator for VLSI chips.

Language:C200

CORE-V Wally is a configurable RISC-V Processor associated with RISC-V System-on-Chip Design textbook. Contains a 5-stage pipeline, support for A, B, C, D, F, M and Q extensions, and optional caches, BP, FPU, VM/MMU, AHB, RAMs, and peripherals.

Language:AssemblyNOASSERTION100