XiangShan

XiangShan's repositories

XiangShan

Open-source high-performance RISC-V processor

Language:ScalaNOASSERTION4989 87 436

XiangShan-doc

Documentation for XiangShan

Language:TeXCC-BY-4.0357 17 35

NEMU

Language:CNOASSERTION244 6 124

difftest

Modern co-simulation framework for RISC-V CPUs

Language:C++MulanPSL-2.0124 5 46

HuanCun

Open-source high-performance non-blocking cache

Language:ScalaNOASSERTION70 10 15

GEM5

Language:C++BSD-3-Clause69 7 26

xs-env

XiangShan Frontend Develop Environment

Language:ShellNOASSERTION47 7 14

CoupledL2

Open-source non-blocking L2 cache

Language:ScalaNOASSERTION35 6 1

nexus-am

Language:C31 2 7

YunSuan

This repo includes XiangShan's function units

Language:ScalaMulanPSL-2.015 5 3

xfuzz

Fuzzing General-Purpose Hardware Designs with Software Fuzzers

Language:ScalaNOASSERTION12 7 7

Deterload

Xiangshan deterministic workloads generator

Language:JavaScriptMulanPSL-2.01100

env-scripts

Scripts for XiangShan

Language:Verilog11 100

CPU2006LiteWrapper

Language:Makefile9 50

Utility

Language:Scala7 60

riscv-isa-sim

Spike, a RISC-V ISA Simulator

Language:CNOASSERTION6 30

ChiselAIA

RISC-V AIA in Chisel

Language:ScalaMulanPSL-2.0400

ready-to-run

Language:Shell4 6 5

rocket-chip

Rocket Chip Generator

Language:ScalaNOASSERTION4 20

gos

Language:Assembly3 30

OpenLLC

Language:ScalaNOASSERTION3 5 1

tl-test-new

The Unified TileLink Memory Subsystem Tester for XiangShan

Language:C++MulanPSL-2.02 4 1

CPU2017LiteWrapper

Language:Makefile1 3 1

nemu_board

Language:Shell1 30

OpenNCB

Open-source Non-coherent CHI Bridge (CHI SN-F to AXI-4 bridge)

Language:Scala1 40

riscv-hyp-tests

A bare-metal application to test specific features of the risc-v hypervisor extension

Language:CGPL-3.0100

riscv-rootfs

Language:C1 20

llvm-project

The LLVM Project is a collection of modular and reusable compiler and toolchain technologies.

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riscv-tests

Language:CNOASSERTION010

XiangShan-home

CC-BY-4.0030