XiangShan (OpenXiangShan)

XiangShan

OpenXiangShan

Organization data from Github https://github.com/OpenXiangShan

Open-source high-performance RISC-V processor

GitHub:@OpenXiangShan

XiangShan's repositories

XiangShan

Open-source high-performance RISC-V processor

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XiangShan-doc

Documentation for XiangShan

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difftest

Modern co-simulation framework for RISC-V CPUs

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HuanCun

Open-source high-performance non-blocking cache

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xs-env

XiangShan Frontend Develop Environment

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CoupledL2

Open-source non-blocking L2 cache

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YunSuan

This repo includes XiangShan's function units

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Deterload

Xiangshan deterministic workloads generator

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env-scripts

Scripts for XiangShan

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riscv-isa-sim

Spike, a RISC-V ISA Simulator

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tl-test-new

The Unified TileLink Memory Subsystem Tester for XiangShan

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XiangShan-User-Guide

The User Guide of XiangShan.

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rocket-chip

Rocket Chip Generator

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ChiselAIA

RISC-V AIA in Chisel

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OpenNCB

Open-source Non-coherent CHI Bridge (CHI SN-F to AXI-4 bridge)

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docs-utils

Utilities for XiangShan Document

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llvm-project

The LLVM Project is a collection of modular and reusable compiler and toolchain technologies.

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qemu

Official QEMU mirror. Please see https://www.qemu.org/contribute/ for how to submit changes to QEMU. Pull Requests are ignored. Please only use release tarballs from the QEMU website.

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