Farrukh Aijaz (FarrukhAijaz)

FarrukhAijaz

User data from Github https://github.com/FarrukhAijaz

GitHub:@FarrukhAijaz

Farrukh Aijaz's repositories

MPC-Lane-Keeping-And-Obstacle-Avoidance

A Model Predictive Algorithm based on an IEEE Journal for Lane Keeping and Obstacle Avoidance on Low Curvature Roads

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3D-Mapping-using-2d-LiDAR

A 3D Mapping Algorithm that generates PointCloud2 Messages which can be used with OctoMap or Cartographer to visualise 3D Voxels on Rviz/Rviz2

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Embedded-C-and-Assembly-Projects

Implemented assembly and embedded C projects encompassing subroutine programming, parameter passing, stack utilization, recursion concepts, parallel I/O, keyboard interfacing, interrupt handling, stepper motor control, general-purpose timer modules, and analog-to-digital conversion.

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FarrukhAijaz

Config files for my GitHub profile.

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GAMA

An application that creates Autosar Classic Software Components in MATLAB Simulink as Models or Subsystmes for each of the Software Components/Sub Components/Units based on a pre defiend user configuration

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LED-Drive-Based-System-using-TM4CGH123-MCU

An LED driver based system that changes the brightness and color of RGB LED based on the detected luminosity

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RISCV-RV32I-Architecture

A standalone Architecture including data paths, Controller and Testbench for the 32 bit Risc V Architecutre

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Runge-Kutta-4-stages-Manaul-Implementation

A manual implementation of runge kutta 4 stages method for SEIRS Model based on IEEE Journal

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servo_publisher

A ROS 2 package that controls a servo motor via PWM signals and continuously rotates the servo smoothly between specified angles while publishing the angle values to a ROS 2 topic.

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Single-Cycle-Multi-Cycle-and-Pipeline-ARM-Based-Processor-Design

Architecure for the Data path and Controller as well as Hazard Units for a 32 bit ARM based Single Cycle, Multi Cycle and Pipelined Based Processor

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VGA-Interface-Design-on-FPGA

A Video Graphics Array Screen was designed and displayed via VGA Interface using an FPGA for sending and receiving packets of data via the FPGA

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