RISC-16 is an open source super simple 16bit cpu core built around the von Neumann architecture.
The project started as an in-between project learning exercice.
It features the following:
- A simple reduced instruction set
- A constant time execution (4 cycles per instruction)
- Support for branching
- Stack management
The project was built using Fusesoc. For details on how to use Fusesoc, refer to the project's documentation.
The project has a dependency on Illusion verilator test, execute the following to synchornize it:
fusesoc library add --sync-type git Verilator-Test https://github.com/Illusion-Graphics/Verilator-Test.git
The core is supplied with a Verilog testbench, to execute it simply run:
fusesoc run --target=test Illusion:RISC16:CPU:1.0
Details on the assembly language can be found in the documentation folder.
A cpu definition is supplied in the documentation folder to use with customasm assembler.