Nick Iliev's repositories
Innovus_NanoRoute_RT01_routed_testcases_Blocking-CLK_path
Detailed routed RT01 and other testcases with Innovus NanoRoute; includes RT01 random blockages. Example routes include CLK paths avoiding all blockages and connecting all DFF pins. All modules are designed with the GSCLK45nm standard cell library. Note that NanoRoute is typically used for routing std cell placements; in this case, custom top-level
ALU_4_bit_4_ops_mitll_fdsoi_process
ALU with 4 operations 1) 4 bit carry look ahead adder 2) 4 bit 1’s complimentary 3) 4 bit 2’s complimentary 4) 4bitAddtraction in 4 bits, done in process mitll_fdsoi, schametics to layout
Analog-CMOS-Systems-and-circuits-for-2D-3D-Localization
This is a novel application of active analog circuits for computing the Cartesian coordinates of points ( targets ) in 2D and 3D space. Two anchors ( points ) are assumed available, with known coordinates. Optical or Infrared Angle-of-Arrival , AOA, (noisy) measurements from each anchor to the uknown target are assumed available.
rng_self_calib
Digital CPU peripheral module for calibration of a pseudo-random-number generator. In CMOS gsclk45 nm, verilog RTL-Compiler (RC) synthesis and Innovus placement and layout.
Spiking_Neural_Synapse_CMOS180
Analog circuits for a Spiking Neuron (and Synapse) in CMOS 180 nm, Cadence ADE XL (Monte Carlo) and ADE_L (Nominal) simulations.