Mehdi Safarpour's repositories
Compressive_Sensing_C_and_MATLAB
C and MATLAB implementation of CS recovery algorithm, i.e. Orthogonal Matching Pursuit, Approximate Message Passing, Iterative Hard Thresholding Algorithms
Algorithmic-SAR-ADC-simulation-files
HSPICE and MATLAB simulation files of a tracking SAR ADC
CUDA-Stereo-Vision-Code
This is CUDA implementation of a well-known stereo vision algorithm
Hexagon_DSP_programming
Repository to learn Hexagon DSP and HVX Programming
LowVoltageDNNonFPGA
Neural Network with ABFT for fault tolerant and low power applications
abft-rescheck
A repository for the code of "A comparison of several fault-tolerance methods for error detection and correction of floating-point errors in matrix multiplication" by Valentin Le Fèvre, Thomas Hérault, Julien Langou and Yves Robert
deep_motion_mag
Tensorflow implementation of Learning-based Video Motion Magnification
FFT_Error_Detection_Energy_Saving
Algorithmic error detection within Fourier context to enable low power-energy solutions based on undervolting
hls4ml
Machine learning in FPGAs using HLS
HotSpot
HotSpot v7.0 is an accurate and fast thermal model suitable for use in architectural studies.
HotSpotMap
A Python-based temperature (thermal) maps generation tool for HotSpot-6.0 (http://lava.cs.virginia.edu/HotSpot/)
LDPC
Simple Matlab function implementing the LDPC soft decoding algorithm, with the log sum product method
lenet5-accelerator
FPGA and GPU acceleration of LeNet5
matmult
A floating-point matrix multiplication implemented in hardware
My-Course-Projects
These are course projects, I've done during my studies. Please do not ask for help and try to understand the method.
os-tutorial
How to create an OS from scratch
SDSoC-Tutorials
SDSoC™ (Software-Defined System-On-Chip) Environment Tutorials
segan
Speech Enhancement Generative Adversarial Network in TensorFlow
SystolicArray
SPICE and Behavioral simulation of systolic array equipped with error detection ABFT
SystolicArray_FPGA
Systolic matrix multiplication kernel implemented on Xilinx PYNQ FPGA board
TPU-Tensor-Processing-Unit
IC implementation of TPU