phase-locked-loop

There are 0 repository under phase-locked-loop topic.

• manili / VSDBabySoC

  VSDBabySoC is a small mixed-signal SoC including PLL, DAC, and a RISCV-based processor named RVMYTH.

  system-on-chipmixed-signaldigital-to-analog-converterrvmythrisc-vphase-locked-loop
  Language:Verilog 31

• lakshmi-sathi / avsdpll1v8_caravel

  PLL x8 clock multiplier IP integrated onto the Efabless Caravel SoC

  open-mpwgoogle-skywater-pdk130nmphase-locked-loop
  Language:Verilog 4

• antonysigma / femptosecond-pulse-trigger-pcb

  Extract the 15MHz clock signal from 400 picosecond pulse train

  clock-synchronizationmicrowave-filtersphase-locked-loopultrafast-opticsmode-locked-laser
  Language:GLSL 1

• DericAugusto / ISN2022_InfTransmission

  Material from the course of Information Transmission at ENSEM - Université de Lorraine.

  bit-error-ratechannel-codingentropyhuffman-codingphase-locked-loopqam-modulationsource-codingtelecommunications
  Language:MATLAB 0