Jayaram Gannabathula (JAYRAM711)

JAYRAM711

User data from Github https://github.com/JAYRAM711

Company:Sathybama Institute of Science and Technology

Location:chennai

Home Page:https://linktr.ee/Jayaram711

GitHub:@JAYRAM711

Jayaram Gannabathula's repositories

100-DAYS-OF-RTL

This Repo contains Codes of RTLs for implementation of various circuit designs using Verilog in Xilinx ISE 14.7 and sometimes Modelsim tools

Language:VerilogStargazers:19Issues:2Issues:0

FSM-MINI-PROJECTS

This Repo contains Source Codes of FSM-BASED implementation of various circuit designs using Verilog in Xilinx ISE 14.7 and sometimes Modelsim tools

Language:VerilogStargazers:3Issues:1Issues:0

INVERTER-DESIGN-AND-ANALYSIS-USING-SKY130PDK

CMOS inverter schematic and layout design and analysis utilizing the skywater 130 nm pdk and numerous open source tools such as Xschem, NGSPICE, MAGIC, Netgen, and so on.

AHB2APB-PROTOCOL-BRIDGE

The AHB to APB Bridge is an AHB slave, providing an interface between the high-speed AHB and the low-power APB. Read and Write transfers on the AHB are converted into equivalent Transfers on the APB

FPGA-PROJECTS

This repository contains the files related to Implementations of various Digital circuits on the NEXYS A7 FPGA Board

Language:TclStargazers:0Issues:1Issues:0

HDL-BITS

This Repo consists codes for some the problem statements from the HDL BITS website and can help you in your journey to learn Verilog from the scratch

Stargazers:0Issues:1Issues:0