stativeboss

Development-of-a-Matrix-Multiplication-unit-using-2D-systolic-array-architecture

1x3_Router

blog_site

CSV-populator-GUI

digitalgarden

Enabling-SDC-swithces-in-Yosys

for_ref_delete

This is a 5-day workshop on RTL Design and Synthesis using open source tools for logic design, simulation, synthesis and technology mapping with Sky130 PDK. (iVerilog, GTKwave, Yosys and Sky130 technology)

for_reference

This repository contains all the information studied and created during the FPGA - Fabric, Design and Architecture workshop. It is primarily focused on a complete FPGA flow using the maximum open-source tools.

FPGA-Fabric_Design_and_Architecture

An intensive 5-day workshop organized by VLSI System Design

MIPS32

SKY130_RTLDSN_WRKSHP

My notes on RTL design in Verilog using SKY130 PDK

poole

The Jekyll Butler. A no frills responsive Jekyll blog theme.

Static_Timing_Analysis

stativeboss.github.io

Build a Jekyll blog in minutes, without touching the command line.

verilog-pcie

Verilog PCI express components