Roa Logic BV

RV12

RISC-V CPU Core

ahb3lite_interconnect

AHB3-Lite Interconnect

ahb3lite_apb_bridge

Parameterised Asynchronous AHB3-Lite to APB4 Bridge.

plic

Platform Level Interrupt Controller

Hamming-ECC

Hamming ECC Encoder and Decoder to protect memories

ahb3lite_memory

Multi-Technology RAM with AHB3Lite interface

adv_dbg_if

Universal Advanced JTAG Debug Interface

ahb3lite_pkg

Common SystemVerilog package used by all RoaLogic IP with AMBA AHB3-Lite interfaces

apb4_mux

APB4 Multiplexor

ahb3lite_timer

RISC-V compliant Timer IP

apb4_gpio

General Purpose IO with APB4 interface

memory

Generic memory implementations

universal_jtag_tap

Universal JTAG TAP Controller

vga_lcd

VGA LCD Core (OpenCores)

vi_systemverilog_syntax

VIM Syntax file for SystemVerilog

riscv_gnu_eclipse

Eclipse Plugin for RISC-V GNU Toolchain

roalogic.github.io

Roa Logic GitHub Pages Site (Top Level)

adv_jtag_bridge

apb4_uart16550

16550 UART with APB4 Interface

ahb3lite_error

AHB module that always generates an error response

ahb3lite_sdram_ctrl

AHB3 Lite SDRAM Controller

apb_error

APB module that always generates an error response

rv_soc

Roa Logic RISC-V SoC

Verilator-simulation

Collection of C++ classes to create Verilator Testbenches

8b10b

8b10b encoder/decoder

OpenOCD

OpenOCD clone for porting RoaLogic Debuggers

riscv-isa-manual

RISC-V Instruction Set Manual

rltheme

Roa Logic Theme for GitHub Pages

rv_c_demos

C demo code to use with the rv_soc

yosys

Yosys Open SYnthesis Suite