arty-s7

There are 0 repository under arty-s7 topic.

timothystotts / fpga-serial-mem-tester-3
A small FPGA and APSoC project of different implementations for testing byte-by-byte a serial flash. Refresh of fpga-serial-mem-tester-1 and -2.
arty-a7 arty-s7 fpga systemonchip systemverilog vhdl pmod zybo-z7
Language:Tcl 4
JeffDeCola / control-fpga-via-raspi-and-webserver
Control a FPGA via a Raspberry Pi and a Webserver.
fpga arty-s7 raspberry-pi raspi verilog golang go webserver gpio pmod xilinx-fpga xilinx-vivado
Language:JavaScript 3
timothystotts / fpga-serial-acl-tester-3
A small FPGA and APSoC project of different implementations for testing Measurement and Activity Events of a SPI accelerometer. Refresh of fpga-serial-acl-tester-1 and -2.
arty-a7 arty-s7 fpga systemverilog verilog vhdl zybo-z7 pmod systemonchip
Language:Tcl 3
Gunmetal-61 / 2021-Hardware
My embedded, FPGA, and computer microarchitecture projects of 2021. This is where I put odd bits and pieces that do not warrant their own repository (yet).
risc-v mcu fpga hardware verilog embedded embedded-systems vivado arty-s7 diligent vhdl
Language:VHDL 2
timothystotts / fpga-colors-tester-3
A small FPGA and APSoC project of multiple implementation for testing and comparing color mixing between discrete RGB LEDs and an OLED RGB display
arty-a7 arty-s7 fpga systemonchip zybo-z7 pmod
Language:Tcl 1
timothystotts / fpga-iic-hygro-tester-3
A small FPGA and APSoC project of different implementations for testing Temperature and Relative Humidity readings of a IIC sensor
arty-a7 arty-s7 fpga verilog zybo-z7 pmod systemonchip
Language:Tcl 1
Florin623 / AXI-Lite-Slave-FPU-IP
FPU that does all the 4 fundamental arithmetic operations made as an AXI-Lite Slave IP in AMD Vivado. IEEE 754 was used. It can be successfully implemented on an Arty S7-50 FPGA board.
arty-s7 axi communication-protocol design digital electronics fpga hardware integrated-circuits interconnect master-slave microblaze microelectronics verilog vitis vivado processor c-programming floating-point intellectual-property
Language:VHDL 0
cas-mls / cpu2
his is a simple CPU architecture that I used to verify that I understand how to use FPGAs, VHDL, and write a CPU using Vivado on Arty S7. This is my largest project to date. Under 1000 Lines of Code.
arty-s7 cpu vhdl vivado
Language:VHDL

arty-s7

timothystotts / fpga-serial-mem-tester-3

JeffDeCola / control-fpga-via-raspi-and-webserver

timothystotts / fpga-serial-acl-tester-3

Gunmetal-61 / 2021-Hardware

timothystotts / fpga-colors-tester-3

timothystotts / fpga-iic-hygro-tester-3

Florin623 / AXI-Lite-Slave-FPU-IP

cas-mls / cpu2