rtl-generation

There are 0 repository under rtl-generation topic.

ollycassidy13 / ReducedLUT
A tool for compression of lookup tables and generation of their hardware files in Verilog for RTL designs
compression fpga hardware-acceleration lookup-table neural-network rtl table-size-reduction verilog rtl-generation hardware-ip ip-generation
Language:C++ 31
graffou / agravic
Simulation platform that enables VHDL-style C++ coding. VCD generation for easy debug. VHDL code generation using C preprocessor. Simple risc-V rv32i SoC example, + Risc-V test suite and gcc bare-metal example. Linux (or WSL) / clang or gcc / risc-v toolchain / quartus required
vhdl simulator risc-v c-plus-plus vcd rtl gtkwave rtl-files arduino vidor fpga rtl-generation de10-lite
Language:C 5

ollycassidy13 / ReducedLUT