rtl-files

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graffou / agravic
Simulation platform that enables VHDL-style C++ coding. VCD generation for easy debug. VHDL code generation using C preprocessor. Simple risc-V rv32i SoC example, + Risc-V test suite and gcc bare-metal example. Linux (or WSL) / clang or gcc / risc-v toolchain / quartus required
vhdl simulator risc-v c-plus-plus vcd rtl gtkwave rtl-files arduino vidor fpga rtl-generation de10-lite
Language:C 3

graffou / agravic