Soham Patel's repositories
16-bit-microprocessor-verilog
A final year undergraduate major project. (Dec 2019 - Mar 2020)
interrupt-controller
A project to implement and test interrupt controller using Questasim software.
Drug-Target-Interaction-Prediction-KNN-
A group project as a part of Pattern Classification course. (Oct 2021 - Nov 2021)
dynamic-pattern-detector-verilog
A project to implement and test dynamic pattern detector using verilog in different ways.
SRAM-memory
A project to implement and test simple SRAM synchronous positive edge memory.
system-verilog-practice
Practice codes and assignments in system verilog.
arduino-ping-pong
A submission task for FOSSE Summer fellowship IIT Bombay. (Feb 2019 - Feb 2019)
arduino-plant-watering-and-weather-track-system
A mini-project as part of prototyping electronics with Arduino course. (Jan 2018 - Feb 2018)
AVR-multifunction-digital-clock
A project as part of Microcontroller and Applications course. (Aug 2018 - Oct 2018)
FPGA-distance-measurment-verilog
A project as part of Digital System Design course. (Oct 2018 - Nov 2018)
EYantra-Robotics-Intership
Summer Trainee Student at CHARUSAT University. (MARCH 2019 - MAY 2019)
fcc_dataanalysis_python
FreeCodeamp Data Analysis with Python
pattern-detector-verilog
A basic 10110 pattern detector using Verilog.
traffic-light-controller-verilog
A project to implement traffic light controller module which has programmable registers along with testbench.
user-defined-clk-verilog
A project to generate user defined jitter, frequency and duty cycle of clock.