Enes Ercin (EnesErcin)

EnesErcin

Geek Repo

Company:Istanbul Technical University

Location:Istanbul Turkey

Home Page:https://enesercin-s01.web.app/

Github PK Tool:Github PK Tool

Enes Ercin's repositories

Convolutional_Neural_Network_wFPGA

FPGA implementation of convolutional neural network with the dataset Fashion mnist

Language:VerilogStargazers:1Issues:1Issues:0

Boron_Encryption

Hardware implementation of ultraligth-weight Boron Encryption and decryption algorithms

Language:VerilogLicense:MITStargazers:0Issues:1Issues:0

cocotb

cocotb, a coroutine based cosimulation library for writing VHDL and Verilog testbenches in Python

Language:PythonLicense:BSD-3-ClauseStargazers:0Issues:0Issues:0

EnesErcin

Profile_Markdown

Stargazers:0Issues:1Issues:0

ExperiencePredict_Machine

This repository is an example of how logistic regression model can be implemented to make a prediction without machine learning libraries.

Language:PythonStargazers:0Issues:0Issues:0

FlyBack_Converter

FlyBack Converter small signal analysis, frequancy responses and error compansator with pulse width modulation. Simulink simulation with matlab scripts.

Language:MATLABStargazers:0Issues:0Issues:0

Image_Preprocessing_wFPGA

FPGA design that can apply basic filters to the image data using block ram.

Language:VerilogLicense:MITStargazers:0Issues:0Issues:0

Img_and_Coe_Exchanger

This repository includes methods that can create .txt files from an image also create an image form specific .txt files.

Language:PythonStargazers:0Issues:0Issues:0

NeuralNetwork_SystemID

PID Tunining with deep neural network from scratch

Language:PythonStargazers:0Issues:1Issues:3

Pipelined_Multipication_Module

An attempt of creating faster multiplication circuit with HDL VHDL

Language:VHDLStargazers:0Issues:1Issues:0

Power_Electronics_GUI

This repository contains a gui application of characteristic features of main power electronic devices.

Language:PythonStargazers:0Issues:0Issues:0
Language:Jupyter NotebookStargazers:0Issues:1Issues:0

Single_Cycle_RISCV_Core

Hardware implementation of single cycle RISC-V core and assembly verifications.

Language:VerilogStargazers:0Issues:0Issues:0

Uart_hardware

Parametric Uart Communication module implemented and tested on fpga hardware.

Language:VerilogStargazers:0Issues:1Issues:0