paul-sanjoy / ALU_VHDL

Arithmetic Logic Unit in VHDL

ALU (Arithmetic Logic Unit)

This project simulates 8 bit ALU (Arithmetic Logic Unit) on FPGA board. It has Arithmetic unit and Logic unit. It can operate on 8 bit inputs and 1 bit carry input and generates a 8 bit output and a 1 bit carry output.

Made with

Xilinx ISE 14.7 and programmed in VHDL.

Output

Contributing

Pull requests are welcome. For major changes, please open an issue first to discuss what you would like to change.

Please make sure to update tests as appropriate.

License

MIT