OpenEDF / verilog-basic

learn the combinational and sequential logic circuit.

verilog_basic

introduction

verilog_base uses Verilog to build 74x series of IP circuits to learn the basic combinational and sequential logic circuits. and build the entire chip step by step. all kinds of ip design.

Compile and simulation command:

$ iverilog -o outputfile readtestxxx.v testbench.v
$ vvp outputfile
$ gtkwave test.cvd &

compiler and simv

$ asciinema ecp
$ exit [wait save and upload to cloud...]

vcs & verdi

vcs & verdi

vivado generate bit and mcs file

create-ip and instance

$ vivado &

TODO:

• add the UVM example and arch
• add the systemverilog example
• add basic digital circuits described using verilg
• add basic ip design
• add pheripherial design code
• add cortex-m0 design amba
• add identify debuge example
• add maba wishbone axi bus
• add new ip
• search synopsys ip
• add gegneral pheripherial ip
• analyze sysnopsys uart ip
• add fifo design