yasnakateb / SdramController

🛠 A SDRAM controller in Verilog HDL

Synchronous dynamic random-access memory (SDRAM) controller

SDRAM is dynamic random access memory (DRAM) with a synchronous interface. It means that SDRAM uses a clock while DRAM does not. The interface has the system bus carrying data between the CPU and the memory controller hub. The memory controller will accept memory requests from the CPU, analyze the requests and dispatch them to the SDRAM in an efficient manner. This SDRAM Controller is simple and only one bank is active at a time.

View of SDRAM controller

Building on macOS

1. Icarus-Verilog can be installed via Homebrew : $ brew install icarus-verilog

2. Download Scansion from here.

3. Clone the repository.

4. Run $ make and type MIPS code to see it in binary form in rams_init_file.hex file.

5. $ make simulate will:

• compile design+TB
• simulate the verilog design

6. $ make display will:

• display waveforms.

Links

1. Design and Verification of SDRAM Controller Based on FPGA
2. FPGA VHDL SDRAM Controller