Kubiran Karakaran's repositories
RISC-V-MYTH-Workshop
This project was done as a part of RISC-V based MYTH (Microprocessor for you in Thirty Hours) workshop organized by Kunal Ghosh and Steve Hoover
Open-Source-Verilog-Projects
This repository contains source code for labs and projects involving FPGA and Verilog based designs
4chipZ80
Z80 system using ATmega as IO/boot controller. 4 chips total.
InventorySystem
Inventory Management System
Vending-Machine
Finite State Machine (FSM) of a custom vending machine implemented in C++ program.
vsdflow
VSDFLOW is an automated solution to programmers, hobbyists and small scale semiconductor technology entrepreneurs who can craft their ideas in RTL language, and convert the design to hardware using VSD (RTL-to-GDS) FLOW. VSDFLOW is completely build using OPHW tools, where the user gives input RTL in verilog. From here on the VSDFLOW takes control, RTL is synthesized (using Yosys). The synthesized netlist is given to PNR tool (Qflow) and finally Sign-off is done with STA tool (using Opentimer). The output of the flow is GDSII layout and performance & area metrics of your design. VSDFLOW also provide hooks at all stages for users working at different levels of design flow. It is tested for 30k instance count design like ARM Cortex-M0, and can be further tested for multi-million instance count using hierarchical or glue logic.
vsdphysicaldesignflow
This repository contains all the information needed to run RTL2GDSII flow using open source EDA tools. OpenLANE is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen, Fault and custom methodology scripts for design exploration and optimization.