Multiplier is one of the most important arithmetic unit in Microprocessors and DSPs and also a major source of power dissipation. Reducing the power dissipation of multipliers is a key to satisfy the overall power budget of various digital circuits and systems. The project elaborates the steps required to design array multiplier. The fundamental units to design a multiplier are adders. The variants of adders used in this project are Carry Save Adder(CSA) and Carry Propagate Adder(CPA). The main objective of our work is to calculate the average power, delay and PDP of 4x4 multipliers. The design of Half adder and Full adder for low power is obtained and the low power units are implemented on the array multiplier and the results are analyzed for better performance. The designs are done using Mentor Graphics tool and are simulated using H-SPICE
