Parallel-Prefix Adder: The Design of CMOS parallel-prefix VLSI Adder

Parallel-Prefix Adder showcases the ability to achieve high-performance adder

This program is operated by HSPICE using 90nm PTM technology at 1V power supply. It employs a parallel-prefix circuit, achieving a minimal delay time of 0.1815ns with a power consumption of 0.9593mW.

32-bit Parallel-Prefix Adder

h0 and 1^st recurrence stage

2^nd-5^th recurrence stage

Sum Block and 2-to-1 MUX

First Prefix-2 for Carry and Transmit(left), 2-to-1 Multiplexer(right)

Inverter and XNOR(XOR) Gate

NOR(OR) and NAND(AND) Gate

I employed the Sparse-2 design to reduce the number of gates in the carry operation (ℎ_i) for the 2-bit adder. The sum is selected by pseudo-carry-in to the group. I used a five-stage approach to construct the 32-bit adder architecture. Each stage is derived using Ling’s transformation, which utilizes the pseudo-carry signal with factor 𝑡_i and combines the pseudo-carry (𝐻_i:j) and transmit (𝑇_i:j), allowing for parallel prefix computation.

Demo

Demo made by Zhe-Wei Pan

Installation

Ensure you have obtained the SSH_key and config from Zhe-Wei Pan and copied it to the following directory:

cp SSH_KEY ~/.ssh/key/SSH_KEY
cp config ~/.ssh/key/config

Install Parallel-Prefix Adder with the following command

git clone git@github.com:QBlobster/parallel-prefix-adder.git

Usage

Make sure to start from C shell by tcsh and set the environment variable for HSPICE.

# Change to C shell
tcsh

# set library path
source /usr/cad/synopsys/CIC/hspice.cshrc

You can modify the spice netlist file in Adder32.sp to analyze the differnet circuits.

Execute vcs to generate the digital waveform to verify the correctness of the parallel-prefix functionality. Next, run hspice to generate the waveform, measure the delay time of A₀ and S₃₁, and record the power consumption:

# Simulate the functionality of 32-bit Parallel-Prefix Adder
vcs -full64 ./tb/Adder32_tb.v Adder32.v -l ./log/comp.log -debug_access+all -o Adder32 -R

# Simulate Spice-level 32-bit Parallel-Prefix Adder
hspice -i Adder32.sp -o ./lis/Adder32.lis

The functinal waveform result will be saved in ./func/Adder32.fsdb. The Spice-level waveform result will be stored in ./lis/Adder32.tr0. You can use wv to view the waveform, and the detailed result can be found in ./lis/Adder32.mt0.

cd lis

cat Adder32.mt0

    #Adder32.mt0
    ...
    t1 =  2.075e-09
    t2 =  2.257e-09
    td =  1.815e-10	#Delay Time
    power =  9.593e-04	#Power
    temper =   27.0000

Contributing

Contributions are always welcome!

Please contact Zhe-Wei Pan.

License

MIT

QBlobster / parallel-prefix-adder