SJTU-ECTL

Emerging Computing Technology Laboratory at SJTU's repositories

ALSRAC

ALSRAC: Approximate Logic Synthesis by Resubstitution with Approximate Care Set

Language:C++16 4 4

VECBEE

VECBEE: A Versatile Efficiency-Accuracy Configurable Batch Error Estimation Method for Greedy Approximate Logic Synthesis

Language:C++8 6 1

GOMIL

GOMIL: Global Optimization of Multiplier by Integer Linear Programming

Language:C++6 4 1

DALS

DALS: Delay-Driven Approximate Logic Synthesis

Language:C++5 60

MECALS

An approximate logic synthesis tool under the maximum error constraint

Language:Verilog4 30

MinAC

MinAC: Minimal-Area Approximate Compressor Design Based on Exact Synthesis for Approximate Multipliers

Language:C++4 40

MinSC

MinSC: An Exact Synthesis-Based Method for Minimal-AreaStochastic Circuits under Relaxed Error Bound

Language:C++4 30

HEDALS

Highly efficient delay-driven approximate logic synthesis

Language:VerilogBSD-3-Clause3 50

STOCA

STOCA: Stochastic Circuit Synthesis by Cube Assignment

Language:C++3 20

BooleanNetwork

A simple data structure for boolean networks.

Language:CMIT2 3 1

EDA-Resource

Repository to store resources. Including benchmarking data, technology mapping libraries, etc.

Language:CMakeGPL-3.02 50

simulator

A small simulator generates random inputs to `blif` circuit to simulator its behavior.

Language:CMIT1 20

StaticTimingAnalysis

Language:C++100

TFASC

TFASC: Target Function Approximation for Stochastic Circuit Minimization

Language:C++1 60

ALFANS-ER

Source codes for two algorithms in ALFANS paper that only involve error rate constraints.

040

ALFANS-ER-EM

Source codes for two algorithms in ALFANS paper that involve both error rate and error magnitues constraints.

Language:C++040

SALODI

SALODI: Simultaneous Area and Latency Optimization for Stochastic Circuits by D Flip-flop Insertion

Language:C++030

SCGen

Language:C++000