Beast code in Giters

jmio's repositories

ECP5_Brieysoc

Briey SoC on ECP5 (ICESugar Pro)

Language:Verilog8 30

paperang_print_PC-G850

Paperang Print From PC-G850 via M5 Stack (as BT Serial Adapter)

Language:C++MIT7 20

PaperangSerial

C# PAPERANG print code via Bluetooth Serial

Language:C#7 1 1

testvex

Briey SoC on Sipeed Tang Primer

Language:Verilog4 10

webg850

PC-G850 verification environment

Language:JavaScriptMIT3 10

CardKB_Serial

Using M5Stack Card Keyboard with UART (TTL Serial)

Language:C++2 10

DCN-150

Digital Caliper DCN-150 Signal and PSoC5 FirmWare

Language:C1 10

micropython

MicroPython - a lean and efficient Python implementation for microcontrollers and constrained systems

Language:CNOASSERTION100

PSoC5LP_PC-G850

Experiment to connect PC-G850 to PSoC5LP

1 10

app80

Assembler pre-processor for Z80.

Language:CMIT010

core_ddr3_controller

A DDR3 memory controller in Verilog for various FPGAs

Language:Verilog000

de10-nano

Absolute beginner's guide to the de10-nano

Apache-2.0000

DOBOTMagician_BBCmicrobit

Running the DOBOT Magician from a BBC microbit

Language:Python010

foboot

Bootloader for Fomu

Language:CNOASSERTION000

jmio.github.io

web page

Language:CSS010

openocd_cmsis-dap_v2

支持CMSIS-DAP v2接口协议，支持ARM、RISCV、ESP32等目标芯片，详见Wiki及release

Language:CNOASSERTION000

orangecrab-examples

Example projects/code for the OrangeCrab

MIT000

orangecrab-hardware

ECP5 breakout board in a feather physical format

Language:HTMLNOASSERTION000

Q24

Utility for Q24 Mitsubishi C-Language Sequencer

Language:CMIT010

SaxonSoc

SoC based on VexRiscv and ICE40 UP5K

Language:ScalaMIT000

sd_device

SD device emulator from ProjectVault

Language:VerilogApache-2.0000

SpinalHDL

Scala based HDL

NOASSERTION000

VexRiscv

A FPGA friendly 32 bit RISC-V CPU implementation

Language:AssemblyMIT000

VexRiscvRegressionData

Used to store heavy data required to run full VexRiscv regressions

000

WindowsForceShutdown

Forceshutdown Command for Windows

Language:C++000