amsacks / OV7670-Video-Processing

Pipelined a real-time edge detection system with a OV7670 camera and Nexys A7 100T FPGA Trainer Board

fifo handshake-protocol nexys-a7 ov7670 pipeline sobel-edge-detector systemverilog verilog

Project Outline

Description: Implement in Verilog add-ons such as grayscaling, sharpening and edge detection to the OV7670 project. Functionality will be verified through self-check testbenches written in SystemVerilog

Updates

(03/17/23): Given RTL works on hardware for procuding only real-time edge detection (sobel filter) with a fixed threshold.

About

Pipelined a real-time edge detection system with a OV7670 camera and Nexys A7 100T FPGA Trainer Board

fifo handshake-protocol nexys-a7 ov7670 pipeline sobel-edge-detector systemverilog verilog

Languages

Language:Verilog 53.5%Language:SystemVerilog 23.0%Language:Shell 13.9%Language:Tcl 7.4%Language:Stata 1.5%Language:VHDL 0.4%Language:Forth 0.2%