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An implementation of the Raft distributed consensus protocol, verified in Coq using the Verdi framework
An implementation of a simple asynchronous message-passing lock server, verified in Coq using the Verdi framework
Verdi framework runtime library
A verified system transformer for serialization of Verdi systems using the Cheerios library.
Created a RISC-V Pipelined processor in SystemVerilog with features like Caches, Prefetching, History Table. Skills employed: SystemVerilog, Verdi, Logic Design, Computer Architecture