jeanthom / gram

DDR3 controller for nMigen (WIP)

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gram

builds.sr.ht status

gram is an nMigen+LambdaSoC port of the LiteDRAM core by enjoy-digital. It currently only targets ECP5+DDR3.

gram is a LambdaConcept project.

Requirements

nMigen + nMigen-SoC + LambdaSoC

gram requires nMigen >= 0.3.

License

2-clause BSD.

About

DDR3 controller for nMigen (WIP)

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Language:Python 90.2%Language:Verilog 4.6%Language:C 3.5%Language:SystemVerilog 0.7%Language:Shell 0.7%Language:Makefile 0.3%