Venkat Kamatham's repositories
OpenROAD-for-Low-cost-ASIC-design-and-Rapid-Innovation
This workshop was organised by IIT Guwahati collabarted with MeitY, NINE Labs, Electronics India.
RTL-to-GDSII-ASIC-design-of-Counter
The objective is to take a simple counter design from the RTL (Register Transfer Level) stage to the GDSII format using Cadence tools with a 90nm Process Design Kit (PDK).. The tools used in this process include Xcelium for simulation and coverage analysis, Genus for synthesis, Innovus for physical design, and Pegasus/PVS for physical verification.