Ayush dixit's repositories
Digital-ASIC-LAB
Verilog Codes for various Design
adruino_extract
Bash script for adruino uno based microcontroller firmware extraction
Baremetal-Arm-programming
Baremetal using KEIL U VISION for STM32F412ZGT6
chisel
Chisel: A Modern Hardware Design Language
CNN_fpga-
CNN on fpga using verilog
snakerobot
Snake Robot using Adruino mega , IR sensor , ESP 32 CAM
Hardware_Codesign_lab
hardware software codesign Lab
Hardware_for_ai
hardware for ai
Hls-BRAM-Integration-
Bram HLS
litex
Build your hardware, easily!
minecraftdixit
Config files for my GitHub profile.
openlane
OpenLANE is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen, Fault and custom methodology scripts for design exploration and optimization.
sequence-detector
Mealy Machine Based Sequence Detector
system-verilog-
sv practice codes
uart-using-verilog
uart implementation using verilog with testbench
verilog-codes-
mini projects