priority-encoder

There are 0 repository under priority-encoder topic.

Vedant-02 / Verilog-HDL-Lab-Experiments
Verilog, standardized as IEEE 1364, is a hardware description language used to model electronic systems. This repository consists of Verilog HDL lab experiments conducted in course EEL2020 Digitial Design at IIT Jodhpur
full-adder 4-bit-parallel-adder binary-to-gray 4-bit-combinational-adder bcd-to-7-segment 4-bit-comparator adder-subtractor carry-look-ahead-adder carry-select-adder 32-bit-fast-adder carry-skip-adder bcd-adder bcd-subtractor binary-multiplier barrel-shifter 32-bit-alu priority-encoder verilog hacktoberfest hacktoberfest2022
Language:Verilog 2
MuballighHossain / Full_Adder_Priority_Encoder_VLSI
encoder fulladder priority-encoder vlsi vlsi-circuits vlsi-design
Language:Verilog 1
CodiieSB / VHDL-PriorityEncoder4x2
A 4x2 priority encoder is a digital circuit that takes four input lines and encodes them into a two-bit binary output based on the priority of the input lines.
4x2 encoder priority priority-encoder vhdl vhdl-examples xilinx-vivado
Language:VHDL 0
levyashvin / verilog_codes
basic implementation of logic structures using verilog (revising github)
d-flipflop full-adder full-subtractor half-subtractor jk-flipflop pipo piso priority-encoder registers sequence-detector sipo siso sr-flip-flop synchronous-counter t-flipflop verilog-testbenches
Language:Verilog 0