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Verilog, standardized as IEEE 1364, is a hardware description language used to model electronic systems. This repository consists of Verilog HDL lab experiments conducted in course EEL2020 Digitial Design at IIT Jodhpur
A 4x2 priority encoder is a digital circuit that takes four input lines and encodes them into a two-bit binary output based on the priority of the input lines.
basic implementation of logic structures using verilog (revising github)