clock-domains

There are 0 repository under clock-domains topic.

• hdl-util / clock-domain-crossing

  Utilities for clock-domain crossing with an FPGA

  clock-synchronizationclock-domain-crossingclock-domainsfpgasystemverilogverilog
  Language:SystemVerilog 5

• w-tr / clock-domain-crossing

  In digital design, it is sometimes necessary to transfer data from one clock domain to another. However because of the nature of how data is stored, there is a probability the transaction will have a setup and hold violation or data is lost because of the different between the domain speeds.

  cdcclockclock-domain-crossingsynchronizationclock-synchronizationclock-domainsclock-design
  Language:VHDL 5

• zslwyuan / Zynq_HLS_DDR_AXI_IPs_Multiple_Clock

  vivadohlszynqdataflowhigh-level-synthesisclock-domains
  Language:VHDL 3

• zslwyuan / Hi-ClockFlow

  Multi-Clock Dataflow Automation and Throughput Optimization in High-Level Synthesis

  clock-domainsdataflowhi-clockflowhigh-level-synthesishlsmulti-clock-dataflowvivadovivado-hls
  1

• MarleyLobao / UVM-mult-clk-domain

  Through a verification environment, this repository uses UVM to handle with multiple clock domains and virtual sequences.

  clock-domainshardware-verificationuvm-virtual-sequence
  Language:SystemVerilog 0