RISCuinho's repositories
awesome-fpga-boards
Second life for FPGA boards which can be repurposed to DYI/Hobby projects
riscuinho.github.io
A scratch on Microcontroller universe
apicula
Project Apicula 🐝: bitstream documentation for Gowin FPGAs
exemplos
Exemplos usados para teste do RISCuinho, os códigos são em assembly ou C/C++, detalhes podem ser obtidos no em https://riscuinho.github.io/categories/exemplos
gowin-easy-linux
Easy setup of GoWin FPGA SDK on Linux. A single script (main_launcher) automates all the critical steps and quickly fires up the IDE.
nextpnr
nextpnr portable FPGA place and route tool
SIMULinho
Simulador integrado iVerilog com interface QT, permite visualizar internamente e controlar a simulação do RISCuinho usando iVerilog
verilog-support
Edit SystemVerilog files (and UVM files) in Vim/gVim
verilog_systemverilog.vim
Verilog/SystemVerilog Syntax and Omni-completion
yosys
Yosys Open SYnthesis Suite
apio-examples
:seedling: Apio examples
arachne-pnr
Place and route tool for FPGAs
chocopy
ChocoPy website
Digital
A digital logic designer and circuit simulator.
emulsiV
A visual simulator, criado por @Guillaum Savaton, for teaching computer architecture using the RISC-V instruction set
iverilog
Icarus Verilog
magic_enum
Static reflection for enums (to string, from string, iteration) for modern C++, work with any enum type without any macro or boilerplate code
riscv-binutils-gdb
RISC-V backports for binutils-gdb. Development is done upstream at the FSF.
riscv-eabi-spec
Proposal for new Embedded ABI (EABI) for use in embedded RISC-V systems.
riscv-formal
RISC-V Formal Verification Framework
riscv-gnu-toolchain
GNU toolchain for RISC-V, including GCC
riscv-v-spec
Working draft of the proposed RISC-V V vector extension
tang-nano-psram
A test of the PSRAM on the Sipeed Tang Nano
venus
RISC-V instruction set simulator built for education