Awesome-FPGA-List

🔥🔥🔥 This repository lists some awesome public HDL and FPGA projects.

Awesome-FPGA-List

Summary

Awesome List
- drom/awesome-hdl : A curated list of amazingly awesome hardware description language projects.
- ben-marshall/awesome-open-hardware-verification : A curated List of Free and Open Source hardware verification tools and frameworks.
- Vitorian/awesome-fpga : A collection of resources on FPGA devices and development in general.
- kelu124/awesome-latticeFPGAs : 📖 List of FPGA Lattice boards using open tools.
- FPGA-Systems/fpga-awesome-list : fpga-awesome-list. Полезные ресурсы по тематике FPGA / ПЛИС.
- hdl/awesome : A curated list of awesome resources for HDL design and verification.
- vhdl/awesome-vhdl : A curated list of awesome VHDL IP cores, frameworks, libraries, software and resources.
- clin99/awesome-eda : A curated list of EDA open source projects.
- iDoka/awesome-fpga-boards : List of Repurposed FPGA boards which getting Second life in DYI or Hobby projects.
- TM90/awesome-hwd-tools : A curated list of awesome open source hardware design tools.
- qninth/awesome-digital-ic : A collection of great digital IC project/tutorial/website etc..
- emanueledelsozzo/awesome-fpga-programming : A curated list of awesome languages and tools to program FPGAs.
- fukatani/awesome-hdl : A curated list of awesome HDL, libraries, typical implementation and references.
- mikeroyal/VHDL-Guide : A guide covering VHDL including the applications, libraries and tools that will make you a better and more efficient with VHDL development.
- mikeroyal/Verilog-SystemVerilog-Guide : Verilog/SystemVerilog Guide. A guide covering Verilog & SystemVerilog including the applications, libraries and tools that will make you a better and more efficient developer by having a better understanding of how hardware works on the lowest level.
- analogdevicesinc/hdl : HDL libraries and projects. wiki.analog.com/resources/fpga/docs/hdl
- analogdevicesinc/hdl : 🌱 Open source ecosystem for open FPGA boards. github.com/FPGAwars/apio/wiki
Learning Resources
- sipeed/TangPrimer-20K-example : AIoT opensource hardware platform. TangPrimer-20K-example project.
- BrunoLevy/learn-fpga : About Learning FPGA, yosys, nextpnr, and RISC-V
- WangXuan95/ZedBoard-Tutorial : Vivado+PetaLinux 系统搭建教程 —— 基于 Zedboard.
Open Development Board
- WangXuan95/UniPlug-FPGA : 体积小、低成本、易用、扩展性强的 FPGA 核心板。

Hardware Description Language

C HDL
- LiteX : The LiteX framework provides a convenient and efficient infrastructure to create FPGA Cores/SoCs, to explore various digital design architectures and createfull FPGA based systems.
Scala HDL
- Chisel : Chisel: A Modern Hardware Design Language. www.chisel-lang.org/
- SpinalHDL : Scala based HDL.
Rust HDL
- Veryl : Veryl: A Modern Hardware Description Language.
- RustHDL : A framework for writing FPGA firmware using the Rust Programming Language.
- VHDL-LS/rust_hdl : This repository contains a fast VHDL language server and analysis library written in Rust.
- yupferris/kaze : An HDL embedded in Rust. kaze provides an API to describe Modules composed of Signals, which can then be used to generate Rust simulator code or Verilog modules.
- dalance/sv-parser : SystemVerilog parser library fully compliant with IEEE 1800-2017.
- dalance/svls : SystemVerilog language server.
- dalance/svlint : SystemVerilog linter.
- vivekmalneedi/veridian : A SystemVerilog Language Server.
- zachjs/sv2v : SystemVerilog to Verilog conversion.
Python HDL
- nMigen : A modern hardware definition language and toolchain based on Python.
- Migen : A Python toolbox for building complex digital hardware.
- MyHDL : MyHDL is a free, open-source package for using Python as a hardware description and verification language.
- Magma : Magma is a hardware design language embedded in python.
- PyRTL : PyRTL provides a collection of classes for pythonic register-transfer level design, simulation, tracing, and testing suitable for teaching and research.
- Veriloggen : Veriloggen: A Mixed-Paradigm Hardware Construction Framework.
- HWT : VHDL/Verilog/SystemC code generator, simulator API written in python/c++.
- HDL21 : Analog Hardware Description Library in Python.

FPGA Applications

Processor Chip
- CPU
  - RISC-V
    - XiangShan (香山) : XiangShan (香山) is an open-source high-performance RISC-V processor project. "Towards Developing High Performance RISC-V Processors Using Agile Methodology". (MICRO 2022)
    - Rocket Chip : Rocket Chip Generator 🚀. This repository contains the Rocket chip generator necessary to instantiate the RISC-V Rocket Core.
    - MoonbaseOtago/vroom : VRoom! RISC-V CPU. A new high-end RISC-V implementation.
    - SpinalHDL/VexRiscv : SpinalHDL/VexRiscv.
    - DarkRISCV : opensouce RISC-V cpu core implemented in Verilog from scratch in one night!
    - stnolting/neorv32 : The NEORV32 RISC-V Processor. 🖥️ A tiny, customizable and highly extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independent VHDL.
    - ZipCPU/zipcpu : The Zip CPU is a small, light-weight, RISC CPU.
    - olofk/serv : SERV - The SErial RISC-V CPU.
    - riscv-mcu/e203_hbirdv2 : The Ultra-Low Power RISC-V Core. doc.nucleisys.com/hbirdv2
    - ultraembedded/riscv : RISC-V CPU Core (RV32IM).
    - ultraembedded/biriscv : 32-bit Superscalar RISC-V CPU.
    - WangXuan95/USTC-RVSoC : An FPGA-based RISC-V CPU+SoC with a simple and extensible peripheral bus. 基于FPGA的RISC-V CPU+SoC，包含一个简单且可扩展的外设总线。
- GPU
  - Ventus(承影) : Ventus(承影) GPGPU. GPGPU processor supporting RISCV-V extension, developed with Chisel HDL.
  - jbush001/NyuziProcessor : Nyuzi is an experimental GPGPU processor focused on compute intensive tasks. It includes a synthesizable hardware design written in System Verilog, an instruction set emulator, an LLVM based C/C++ compiler, software libraries, and tests.
IP Module
- IP Generator
  - lnis-uofu/OpenFPGA : The award-winning OpenFPGA framework is the first open-source FPGA IP generator with silicon proofs supporting highly-customizable FPGA architectures. OpenFPGA provides complete EDA support for customized FPGAs, including Verilog-to-bitstream generation and self-testing verification. OpenFPGA opens the door to democratizing FPGA technology and EDA techniques with agile prototyping approaches and constantly evolving EDA tools for chip designers and researchers. openfpga.readthedocs.io/en/master/. "OpenFPGA: An Open-Source Framework for Agile Prototyping Customizable FPGAs". (IEEE Micro, 2020)
- PCIe Module
  - WangXuan95/Xilinx-FPGA-PCIe-XDMA-Tutorial : Xilinx FPGA PCIe 保姆级教程 ——基于 PCIe XDMA IP核。
  - Reconfigurable-Computing/Xilinx-FPGA-PCIe-XDMA-Tutorial : Xilinx FPGA PCIe 保姆级教程 ——基于 PCIe XDMA IP核。
  - enjoy-digital/litepcie : LitePCIe provides a small footprint and configurable PCIe core.
  - alexforencich/verilog-pcie : Verilog PCI Express Components Readme.
- DDR Module
  - ultraembedded/core_ddr3_controller : A DDR3 memory controller in Verilog for various FPGAs.
  - WangXuan95/FPGA-DDR-SDRAM : An AXI4-based DDR1 controller to realize mass, cheap memory for FPGA. 基于FPGA的DDR1控制器，为低端FPGA嵌入式系统提供廉价、大容量的存储。
  - adibis/DDR2_Controller : DDR2 memory controller written in Verilog.
  - BrianHGinc/BrianHG-DDR3-Controller : DDR3 Controller v1.60, 16 read/write ports, configurable widths, priority, auto-burst size & cache on each port. VGA/HDMI multiwindow video controller with alpha-blended layers. Docs & TBs included.
  - someone755/ddr3-controller : A DDR3(L) PHY and controller, written in Verilog, for Xilinx 7-Series FPGAs.
  - WangXuan95/FPGA-DDR-SDRAM : An AXI4-based DDR1 controller to realize mass, cheap memory for FPGA. 基于FPGA的DDR1控制器，为低端FPGA嵌入式系统提供廉价、大容量的存储。
- Ethernet Module
  - alexforencich/verilog-ethernet : Verilog Ethernet components for FPGA implementation.
- WIFI Module
  - openwifi : open-source IEEE 802.11 WiFi baseband FPGA (chip) design: driver, software.
- UART Module
  - ZipCPU/wbuart32 : A simple, basic, formally verified UART controller.
  - WangXuan95/Verilog-UART : 3 independent modules for FPGA: UART receiver, UART transmitter, UART interactive debugger. 3个独立模块：UART接收器、UART发送器、UART交互式调试器。
- USB Module
  - WangXuan95/FPGA-USB-Device : An FPGA-based USB full-speed device core to implement USB-serial, USB-camera, USB-audio, USB-disk, USB-keyboard, etc. It requires only 3 FPGA common IOs rather than additional chips. 基于FPGA的USB full-speed device端控制器，可实现USB串口、USB摄像头、USB音频、U盘、USB键盘等设备，只需要3个FPGA普通IO，而不需要额外的接口芯片。
- CAN-bus Module
  - WangXuan95/FPGA-CAN : An FPGA-based lightweight CAN bus controller. 基于FPGA的轻量级CAN总线控制器。
- AXI Module
  - pulp-platform/axi : AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication.
- HDMI Module
  - hdl-util/hdmi : Send video/audio over HDMI on an FPGA. purisa.me/blog/hdmi-released/
- SD-card Module
  - WangXuan95/FPGA-SDcard-Reader : An FPGA-based SD-card reader to read files from FAT16 or FAT32 formatted SD-cards. 基于FPGA的SD卡读取器，可以从FAT16或FAT32格式的SD卡中读取文件。
  - WangXuan95/FPGA-SDcard-Reader-SPI : An FPGA-based SD-card reader via SPI bus, which can read files from FAT16 or FAT32 formatted SD-cards. 基于FPGA的SD卡读取器(通过SPI总线)，可以从FAT16或FAT32格式的SD卡中读取文件。
  - WangXuan95/FPGA-SDfake : Imitate SDcard using FPGAs. 使用FPGA模拟(伪装) SD卡。
- NFC Module
  - WangXuan95/FPGA-NFC : Build an NFC (RFID) card reader using FPGA and simple circuit instead of RFID-specfic chip. 用FPGA+分立器件电路搭建一个NFC(RFID)读卡器，不需要专门的RFID芯片。
- SATA Module
  - WangXuan95/FPGA-SATA-HBA : A SATA host (HBA) core based on Xilinx FPGA with GTH. Easy to read/write hard disk. 一个基于Xilinx FPGA中的GTH的SATA host控制器，用来读写硬盘。
- DAC Module
  - WangXuan95/FPGA-DAC-R2R-PWM : FPGA-based 14bit DAC with resistance network and PWM.
Camera Firmware
- apertus-open-source-cinema/axiom-firmware : AXIOM Beta Software. Firmware required to boot & operate the apertus° AXIOM Beta Camera. "微信公众号「OpenFPGA」《世界上最伟大的开源作品-基于FPGA的开源摄影机--Axiom Camera》"。
Spiking Neural Network
- ChFrenkel/tinyODIN : tinyODIN Low-Cost Digital Spiking Neural Network (SNN) Processor.
- ChFrenkel/ODIN : ODIN Spiking Neural Network (SNN) Processor.
- ChFrenkel/ReckOn : ReckOn: A Spiking RNN Processor Enabling On-Chip Learning over Second-Long Timescales.
Convolutional Neural Network
- Xilinx/Vitis-AI : Vitis AI offers a unified set of high-level C++/Python programming APIs to run AI applications across edge-to-cloud platforms, including DPU for Alveo, and DPU for Zynq Ultrascale+ MPSoC and Zynq-7000. It brings the benefits to easily port AI applications from cloud to edge and vice versa. 10 samples in VART Samples are available to help you get familiar with the unfied programming APIs. Vitis-AI-Library provides an easy-to-use and unified interface by encapsulating many efficient and high-quality neural networks.
- tensil-ai/tensil : Open source machine learning accelerators. www.tensil.ai
- 19801201/SpinalHDL_CNN_Accelerator : CNN accelerator implemented with Spinal HDL.
- ZFTurbo/MobileNet-in-FPGA : Generator of verilog description for FPGA MobileNet implementation.
- MasLiang/CNN-On-FPGA : This is the code of the CNN on FPGA.But this can only be used for reference at present for some files are write coarsly using ISE.
- PipeCNN : PipeCNN is an OpenCL-based FPGA Accelerator for Large-Scale Convolutional Neural Networks (CNNs).
Object Detection
- dhm2013724/yolov2_xilinx_fpga : YOLOv2 Accelerator in Xilinx's Zynq-7000 Soc(PYNQ-z2, Zedboard and ZCU102). (硕士论文 2019, 电子技术应用 2019, 计算机科学与探索 2019)
- Yu-Zhewen/Tiny_YOLO_v3_ZYNQ : Implement Tiny YOLO v3 on ZYNQ. "A Parameterisable FPGA-Tailored Architecture for YOLOv3-Tiny". (ARC 2020)
- HSqure/ultralytics-pt-yolov3-vitis-ai-edge : This demo is only used for inference testing of Vitis AI v1.4 and quantitative compilation of DPU. It is compatible with the training results of ultralytics/yolov3 v9.5.0 (it needs to use the model saving method of Pytorch V1.4).
- mcedrdiego/Kria_yolov3_ppe : Kria KV260 Real-Time Personal Protective Equipment Detection. "Deep Learning for Site Safety: Real-Time Detection of Personal Protective Equipment". (Automation in Construction 2020)
- xlsjdjdk/Ship-Detection-based-on-YOLOv3-and-KV260 : This is the entry project of the Xilinx Adaptive Computing Challenge 2021. It uses YOLOv3 for ship target detection in optical remote sensing images, and deploys DPU on the KV260 platform to achieve hardware acceleration.
- Pomiculture/YOLOv4-Vitis-AI : Custom YOLOv4 for apple recognition (clean/damaged) on Alveo U280 accelerator card using Vitis AI framework.
- mkshuvo2/ZCU104_YOLOv3_Post_Processing : Tensor outputs form Vitis AI Runner Class for YOLOv3.
- puffdrum/v4tiny_pt_quant : quantization for yolo with xilinx/vitis-ai-pytorch.
- chanshann/LITE_YOLOV3_TINY_VITISAI : LITE_YOLOV3_TINY_VITISAI.
- LukiBa/zybo_yolo : YOLO example implementation using Intuitus CNN accelerator on ZYBO ZYNQ-7000 FPGA board.
- matsuda-slab/YOLO_ZYNQ_MASTER : Implementation of YOLOv3-tiny on FPGA.
- AramisOposich/tiny_YOLO_Zedboard : tiny_YOLO_Zedboard.
- FerberZhang/Yolov2-FPGA-CNN- : A demo for accelerating YOLOv2 in xilinx's fpga PYNQ.
- Prithvi-Velicheti/FPGA-Accelerator-for-TinyYolov3 : An FPGA-Accelerator-for-TinyYolov3.
- ChainZeeLi/FPGA_DPU : This project is to implement YOLO v3 on Xilinx FPGA with DPU.
- xbdxwyh/yolov3_fpga_project : yolov3_fpga_project.
- ZLkanyo009/Yolo-compression-and-deployment-in-FPGA : 基于FPGA量化的人脸口罩检测。
- xiying-boy/yolov3-AX7350 : 基于HLS_YOLOV3的驱动文件。
- himewel/yolowell : A set of hardware architectures to build a co-design of convolutional neural networks inference at FPGA devices.
- embedeep/Free-TPU : Free TPU for FPGA with Lenet, MobileNet, Squeezenet, Resnet, Inception V3, YOLO V3, and ICNet. Deep learning acceleration using Xilinx zynq (Zedboard or ZC702 ) or kintex-7 to solve image classification, detection, and segmentation problem.
- yarakigit/design_contest_yolo_change_ps_to_pl : Converts pytorch yolo format weights to C header files for bare-metal (FPGA implementation).
- adamgallas/fpga_accelerator_yolov3tiny : fpga_accelerator_yolov3tiny.
- ylk678910/tiny-yolov3-fpga : Use an all-programmable SoC board to implement locating and tracking tasks. The hardware algorithm, a row-stationary-like strategy, can parallel calculate and reduce the storage buffer area on FPGA.
- zhen8838/K210_Yolo_framework : Yolo v3 framework base on tensorflow, support multiple models, multiple datasets, any number of output layers, any number of anchors, model prune, and portable model to K210 !
- SEASKY-Master/SEASKY_K210 : K210 PCB YOLO.
- SEASKY-Master/Yolo-for-k210 : Yolo-for-k210.
- TonyZ1Min/yolo-for-k210 : keras-yolo-for-k210.
- vseasky/yolo-for-k210 : Yolo-for-k210.
- shilicon/kr260_robotic_arm : A robotic arm controller design based on AMD/Xilinx KR260 FPGA dev-kit. 这是一个在AMD/Xilinx Kria KR260 FPGA板卡上实现机械臂抓取物体的工程。
Visual SLAM
- sdoira/U96-SLAM : Visual SLAM on Ultra96-V2.
Image Compression
- WangXuan95/FPGA-JPEG-LS-encoder : An FPGA-based JPEG-LS encoder, which provides lossless and near-lossless image compression with high compression ratios. 基于FPGA的JPEG-LS编码器，可实现高压缩率的无损/近无损图象压缩。
- WangXuan95/FPGA-MPEG2-encoder : FPGA-based high performance MPEG2 encoder for video compression. 基于 FPGA 的高性能 MPEG2 视频编码器，可实现视频压缩。
- WangXuan95/UH-JLS : FPGA-based Ultra-High Throughput JPEG-LS encoder, which provides lossless image compression. 一个超高性能的FPGA JPEG-LS编码器，用来进行无损图象压缩。
Motor Control
- WangXuan95/FPGA-FOC : FPGA-based Field Oriented Control (FOC) for driving BLDC/PMSM motor. 基于FPGA的FOC控制器，用于驱动BLDC/PMSM电机。
Fixed-point
- WangXuan95/Verilog-FixedPoint : A Verilog fixed-point lib: custom bit width, arithmetic, converting to float, with single cycle & pipeline version. 一个Verilog定点数库，提供算术运算、与浮点数的互相转换，包含单周期和流水线两种实现。

Awesome-FPGA-List

Contents

Summary

Awesome List

Learning Resources

Open Development Board

Hardware Description Language

C HDL

Scala HDL

Rust HDL

Python HDL

FPGA Applications

Processor Chip

CPU

RISC-V

GPU

IP Module

IP Generator

PCIe Module

DDR Module

Ethernet Module

WIFI Module

UART Module

USB Module

CAN-bus Module

AXI Module

HDMI Module

SD-card Module

NFC Module

SATA Module

DAC Module

Camera Firmware

Spiking Neural Network

Convolutional Neural Network

Object Detection

Visual SLAM

Image Compression

Motor Control

Fixed-point

Blogs

About