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Verilog, standardized as IEEE 1364, is a hardware description language used to model electronic systems. This repository consists of Verilog HDL lab experiments conducted in course EEL2020 Digitial Design at IIT Jodhpur
Interactive website for demonstrating or simulating binary multiplication via pencil-and-paper method, Booth's algorithm, and extended Booth's algorithm (bit-pair recoding)
create a 4-bit multiplier with VHDL language