Verilog-HDL-Lab-Experiments
Verilog, standardized as IEEE 1364, is a hardware description language used to model electronic systems. This repository consists of verilog HDL based lab experiments conducted in course EEL2020 Digitial Design at IIT Jodhpur.
The list of experiments mentioned in this repository are as follows:
- Half adder
- Full adder
- Four bit Parallel adder
- Binary to Gray code converter
- Gray to binary code converter
- Binary to BCD converter
- BCD to 7-segment display decoder
- Four bit Adder-Subtractor
- Four bit Comparator
- 32-bit fast adders (carry look ahead, carry skip, carry select)
- BCD Adder
- BCD Subtractor
- Binary Multiplier (3 bit x 3 bit)
- Barrel Shifter
- 32-bit ALU
- Priority encoder
- D flip-flop(synchronous & asynchronous reset)