bcd-subtractor

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Vedant-02 / Verilog-HDL-Lab-Experiments
Verilog, standardized as IEEE 1364, is a hardware description language used to model electronic systems. This repository consists of Verilog HDL lab experiments conducted in course EEL2020 Digitial Design at IIT Jodhpur
full-adder 4-bit-parallel-adder binary-to-gray 4-bit-combinational-adder bcd-to-7-segment 4-bit-comparator adder-subtractor carry-look-ahead-adder carry-select-adder 32-bit-fast-adder carry-skip-adder bcd-adder bcd-subtractor binary-multiplier barrel-shifter 32-bit-alu priority-encoder verilog hacktoberfest hacktoberfest2022
Language:Verilog 3