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Code, documentation, schematics, notes for my Ben Eater inspired breadboard computer and emulator
VHDL project to run a simple 8-bit computer very similar to the one built by Ben Eater (see https://eater.net)
Documentation of my 8-bit computer build
A very simple computer written in Verilog, with a Python test bench
SAP-1 implementation in VHDL for the Sipeed Tang Nano 9k
Verilog implementation of SAP-1 computer architecture
A C++ Implementation of X-Bit Computer SAP-X Architecture Virtualization
The Simple-As-Possible (SAP)-1 computer is a very basic model of a microprocessor explained by Albert Paul Malvino. The SAP-1 design contains the basic necessities for a functional Microprocessor. Its primary purpose is to develop a basic understanding of how a microprocessor works, interacts with memory and other parts of the system like input and output. The instruction set is very limited and is simple.