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ucb-bar
/
riscv-mini
Simple RISC-V 3-stage Pipeline in Chisel
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Stargazers:
512
Watchers:
40
Issues:
28
Forks:
103
ucb-bar/riscv-mini Issues
Problems related to asSint type conversion to verilog file (.sv)
Updated
2 months ago
Comments count
1
some problem about the code of test
Closed
4 months ago
Comments count
2
Is riscv-mini a single-cycle-processor?
Updated
4 months ago
Comments count
1
Cannot run program "z3"CreateProcess error=2, system cant find the file specified
Closed
4 months ago
Comments count
1
encountered error when performing make"firtool returned a non-zero exit code. Note that this version of Chisel (5.0.0) was published against firtool version 1.40.0."
Closed
4 months ago
Comments count
3
How to Generate Tile.fir or Tile.mlir in generated-src after Running `make`?
Updated
6 months ago
NastiArbiter IO forgot wrap in IO
Updated
6 months ago
Test hexfile creation documentation
Closed
10 months ago
Comments count
1
Strobe writes broken in TileTester.
Updated
2 years ago
Failed all formal verification.
Closed
2 years ago
Comments count
2
[RFC] Upgrade to User-level ISA v2.2 and Privileged Architecture v1.10
Updated
2 years ago
Comments count
2
Is this a BUG in TileTester.scala?
Closed
2 years ago
Comments count
3
Synchronous read?
Closed
2 years ago
Comments count
1
How do I add a new register under the source code of src, and then use GTKWave to see this register when viewing the waveform?
Closed
2 years ago
Comments count
1
Does this code have a bug?
Closed
2 years ago
Proposal to Update Project to Latest Chisel
Closed
2 years ago
Comments count
4
after I use quartus II 9.0 to compile Title.v successfully, but I double click ALUArea::alu module turn on error below attached
Closed
2 years ago
Comments count
1
Generated Tile.v won't compile
Closed
2 years ago
Comments count
4
Error in make command
Closed
2 years ago
Comments count
4
Building priv-1.7 riscv-toolchain fails
Closed
2 years ago
Comments count
3
Underlying behavior of each module
Closed
2 years ago
Add command line argument to verilator to support very wide wires
Closed
2 years ago
Is this core based on zcale ?
Closed
2 years ago
make run-tests errors
Closed
2 years ago
riscv-mini doesn't support print and declare the float data type variable
Closed
3 years ago
Comments count
1
Test directory naming simplification introduces collisions
Closed
4 years ago
Comments count
1
instruction doesn't appear in spec?
Closed
6 years ago
Comments count
2
Running simulation with other programs?
Closed
6 years ago
Comments count
1