ucb-bar / riscv-mini

Simple RISC-V 3-stage Pipeline in Chisel

Geek Repo:Geek Repo

Github PK Tool:Github PK Tool

How to Generate Tile.fir or Tile.mlir in generated-src after Running `make`?

Stevengre opened this issue · comments

I'm trying to generate either a Tile.fir or Tile.mlir file in the generated-src directory after running the make command. However, I'm facing an issue.

Here's what I've done so far:

I ran make in the terminal as usual.
Then, I tried changing emitSystemVerilogFile to emitCHIRRTL in the code.
After that, I executed sbt 'runMain mini.Main'.
Despite these steps, I'm not seeing the expected Tile.fir or Tile.mlir files in the generated-src directory. It's quite puzzling for me.

Thanks in advance for any help or guidance you can provide!

Go to see #67 which modify Makefile and pass an argument --dump-fir to ChiselStage. emitSystemVerilog(File) is just a common API to generate something like SV or Firrtl file so there is no need to modify source code.