ucb-bar / riscv-mini

Simple RISC-V 3-stage Pipeline in Chisel

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Is this a BUG in TileTester.scala?

LingZichao opened this issue · comments

id := dut.io.nasti.aw.bits.id

In my view,aw shall be ar , which stands for read address channel in AXI

Could be. What happens if you change it?

Uhhh ... Because there is no out-of-order transaction , so it just maybe a ctrl c+v bug and no negative impact. : )

Uhhh ... Because there is no out-of-order transaction , so it just maybe a ctrl c+v bug and no negative impact. : )

feel free to still make a PR. Seems like something that should be fixed