ucb-bar / riscv-mini

Simple RISC-V 3-stage Pipeline in Chisel

Geek Repo:Geek Repo

Github PK Tool:Github PK Tool

Synchronous read?

AwaniK opened this issue · comments

Do the memory and regfile have synchronous read operation?

Do the memory and regfile have synchronous read operation?

The regfile is using a combinatorial read memory. The cache uses a synchronous read memory.

Changing the read latency on the register file would require some pipeline changes.