ucb-bar / riscv-mini

Simple RISC-V 3-stage Pipeline in Chisel

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after I use quartus II 9.0 to compile Title.v successfully, but I double click ALUArea::alu module turn on error below attached

zhouxs1023 opened this issue · comments

after I use quartus II 9.0 to compile Title.v successfully, but I double click ALUArea::alu module turn on error as below:
360-16581118485047
if alu module have a bug ??

It was fine with Vivado. ALUArea may not be friendly to FPGA since it's optimized for ASIC. Can you try ALUSimple instead?
https://github.com/ucb-bar/riscv-mini/blob/master/src/main/scala/Config.scala#L13