ucb-bar / riscv-mini

Simple RISC-V 3-stage Pipeline in Chisel

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Underlying behavior of each module

azimgivron opened this issue · comments

commented

Hi,

I've started coding Chisel the past few weeks and I have to work on the risc v mini processor. I am having troubles following which signal is used for what in code. I also do not understand how is the freechips.rocketchip.config suppose to work. So my question is: do you have a report or a commented version of the code that contains the description of the intern signals of each module ?

Thank you