Does this code have a bug?

[rongfu.leng]

in ALU.scala file:
define below:
val ALU_ADD = 0.U(4.W)
val ALU_SUB = 1.U(4.W)
io.sum := io.A + Mux(io.alu_op(0), -io.B, io.B)
in mux ,if io.alu_op(0) is 0 then alu_op is ALU_ADD then Mux(io.alu_op(0), io.B, -io.B) ?