Generated Tile.v won't compile

[Hob Den]

Hi.

I was trying to follow your instructions on README.md to get verilator tests running, before encountering the following error

hob:riscv-mini/ (master) $ make verilator
verilator --cc --exe --assert -Wno-STMTDLY -O3 --trace --top-module Tile -Mdir /home/hob/Programs/test/riscv-mini/generated-src/VTile.csrc -CFLAGS "-std=c++11 -Wall -Wno-unused-variable -include /home/hob/Programs/test/riscv-mini/generated-src/VTile.csrc/VTile.h"  -o /home/hob/Programs/test/riscv-mini/VTile /home/hob/Programs/test/riscv-mini/generated-src/Tile.v /home/hob/Programs/test/riscv-mini/src/main/cc/top.cc /home/hob/Programs/test/riscv-mini/src/main/cc/mm.cc
%Error: /home/hob/Programs/test/riscv-mini/generated-src/Tile.v:3397: syntax error, unexpected INTEGER NUMBER, expecting IDENTIFIER
%Error: Exiting due to 1 error(s)
%Error: Command Failed /usr/bin/verilator_bin --cc --exe --assert -Wno-STMTDLY -O3 --trace --top-module Tile -Mdir /home/hob/Programs/test/riscv-mini/generated-src/VTile.csrc -CFLAGS '-std=c++11 -Wall -Wno-unused-variable -include /home/hob/Programs/test/riscv-mini/generated-src/VTile.csrc/VTile.h' -o /home/hob/Programs/test/riscv-mini/VTile /home/hob/Programs/test/riscv-mini/generated-src/Tile.v /home/hob/Programs/test/riscv-mini/src/main/cc/top.cc /home/hob/Programs/test/riscv-mini/src/main/cc/mm.cc
Makefile:28: recipe for target '/home/hob/Programs/test/riscv-mini/VTile' failed
make: *** [/home/hob/Programs/test/riscv-mini/VTile] Error 10

The sbt tests fail as a result too.

It says that there's a syntax error on the 3397th line of Tile.v, which is

          $fwrite(32'h80000002,"PC: %h, INST: %h, REG[%d] <- %h\n",ew_pc,ew_inst,_T_296,_T_298); // @[Datapath.scala 172:11]

However if I change fwrite to display and delete that 32'h80000002 it compiles without problem.

---

My setup:

$ git clone https://github.com/ucb-bar/riscv-mini.git 
$ cd riscv-mini
$ make  # it tells me there's 68 feature warnings
$ make verilator

My environment:

• Ubuntu 16.04
• Verilator 3.874 2015-06-06 rev verilator_3_872-20-g0d43051 (just the one from apt install)
• Scala version 2.11.6 (OpenJDK 64-Bit Server VM, Java 1.8.0_171).

Could you tell my if there's anything I's wrong or missed?
Thank you very much.

[Donggyu Kim]

It's odd... Why don't you try a newer version of verilator? Mine is Verilator 3.920 2018-02-01 rev verilator_3_918-16-g13d11b0

[hfming225]

hi, I have a some question about this.
After generate the VTile, I use make run-tests,it shows

and when i use ./VTile median.riscv.hex,it shows that

i don't know what is the problem about this.

[Hob Den]

@donggyukim
After upgrading to Verilator 3.920, everything worked without any problem.

Thanks!

[Zhouwk7]

hi, I have a some question about this.
After generate the VTile, I use make run-tests,it shows

and when i use ./VTile median.riscv.hex,it shows that

i don't know what is the problem about this.
Ｈｉ， @hfming225 ， I have meet the same problem, do you figure out it?