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vsdip / vsdflow
VSDFLOW is an automated solution to programmers, hobbyists and small scale semiconductor technology entrepreneurs who can craft their ideas in RTL language, and convert the design to hardware using VSD (RTL-to-GDS) FLOW. VSDFLOW is completely build using OPHW tools, where the user gives input RTL in verilog. From here on the VSDFLOW takes control, RTL is synthesized (using Yosys).
rtl programmer vsdip semiconductor opensource synthesis yosys qflow magic graywolf qrouter netgen opentimer opensta blifffanout tcl physicaldesign static sta scripting-language
Language:Coq 13

vsdip / vsdflow