nelsoncsc / basic_uvmc

A simple testbench with two refmods using UVM Connect

systemverilog-hdl uvm functional-verification systemc

#basic_uvmc: a simple testbench with two refmods using UVM Connect https://sistenix.com/basic_uvmc.html

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A simple testbench with two refmods using UVM Connect

systemverilog-hdl uvm functional-verification systemc

MIT License

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Language:SystemVerilog 64.1%Language:Makefile 19.5%Language:C++ 16.5%