enjoy-digital

enjoy-digital

Geek Repo

Company:EnjoyDigital

Location:France

Home Page:http://www.enjoy-digital.fr

Github PK Tool:Github PK Tool


Organizations
betrusted-io
litex-hub
timvideos

enjoy-digital's repositories

litex

Build your hardware, easily!

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litepcie

Small footprint and configurable PCIe core

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litedram

Small footprint and configurable DRAM core

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liteeth

Small footprint and configurable Ethernet core

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usb3_pipe

USB3 PIPE interface for Xilinx 7-Series

Language:VerilogLicense:BSD-2-ClauseStargazers:178Issues:29Issues:27

litescope

Small footprint and configurable embedded FPGA logic analyzer

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pcie_screamer

PCIe Screamer - TLPs experiments...

Language:CLicense:BSD-2-ClauseStargazers:155Issues:18Issues:10

litesata

Small footprint and configurable SATA core

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litesdcard

Small footprint and configurable SDCard core

Language:PythonLicense:NOASSERTIONStargazers:107Issues:13Issues:12

colorlite

Take control of your Colorlight FPGA board with LiteX/LiteEth :)

Language:PythonLicense:BSD-2-ClauseStargazers:91Issues:10Issues:8

liteiclink

Small footprint and configurable Inter-Chip communication cores

Language:PythonLicense:NOASSERTIONStargazers:51Issues:11Issues:8

litex-acorn-baseboard

LiteX development baseboards arround the SQRL Acorn.

Language:PythonLicense:NOASSERTIONStargazers:49Issues:14Issues:8

litejesd204b

Small footprint and configurable JESD204B core

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litex_rp2040_pmod_test

Test of a RP2040 PMOD attached to a LiteX SoC.

xtrx_julia

XTRX LiteX/LitePCIe based design for Julia Computing

Language:CLicense:BSD-2-ClauseStargazers:21Issues:7Issues:13

thunderscope

LiteX based FPGA gateware for Thunderscope.

litex_verilog_axi_test

Integration test of Verilog AXI modules (https://github.com/alexforencich/verilog-axi) with LiteX.

openFPGALoader

Universal utility for programming FPGA

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learn-fpga

Learning FPGA, yosys, nextpnr, and RISC-V

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litex_naxriscv_test

NaxRiscv integration test with LiteX

litex_soc_gen_test

Test of LiteX standalone SoC generator.

litepcie_ptm_test

LitePCIe PTM support / test repo.

litex_limesdr_mini_v2_test

LiteX alternative SoC/Gateware for the LimeSDR Mini 2.0

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acorn_pcie_compute_test

PCIe compute test on Acorn CLE 215+.

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corescore

CoreScore

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litex_mister_test

Simplification test of MiSTer with LiteX to try to help/contribute to MiSTeX project.

openocd

Spen's Official OpenOCD Mirror (no pull requests)

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litex_64bit_addressing_test

Test/PoC of 64-bit addressing in LiteX.

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litex_verilog_axis_test

Integration test of Verilog AXI Stream modules (https://github.com/alexforencich/verilog-axis) with LiteX.

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openfpga-pong

FPGA Pong implementation, specifically for the Analogue Pocket

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